NXP Semiconductors /LPC15xx /DMA /INTENSET0

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as INTENSET0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SET0)SET0 0 (SET1)SET1 0 (SET2)SET2 0 (SET3)SET3 0 (SET4)SET4 0 (SET5)SET5 0 (SET6)SET6 0 (SET7)SET7 0 (SET8)SET8 0 (SET9)SET9 0 (SET10)SET10 0 (SET11)SET11 0 (SET12)SET12 0 (SET13)SET13 0 (SET14)SET14 0 (SET15)SET15 0 (SET16)SET16 0 (SET17)SET17 0RESERVED

Description

Interrupt Enable read and Set for all DMA channels.

Fields

SET0

0

SET1

0

SET2

0

SET3

0

SET4

0

SET5

0

SET6

0

SET7

0

SET8

0

SET9

0

SET10

0

SET11

0

SET12

0

SET13

0

SET14

0

SET15

0

SET16

0

SET17

0

RESERVED

Reserved.

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